mmCM3_CM_ICSC_CONTROL_BASE_IDX 5055 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM3_CM_ICSC_CONTROL_BASE_IDX                                                                 2
mmCM3_CM_ICSC_CONTROL_BASE_IDX 6097 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM3_CM_ICSC_CONTROL_BASE_IDX                                                                 2
mmCM3_CM_ICSC_CONTROL_BASE_IDX 5159 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM3_CM_ICSC_CONTROL_BASE_IDX                                                                 2