mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 5115 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 6165 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 5227 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2