mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 5127 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 6177 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 5239 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2