mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 4856 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 5795 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 4857 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2