mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 4636 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 5587 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 4649 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2