mmCM2_CM_DGAM_RAMA_END_CNTL2_G 4653 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0f04
mmCM2_CM_DGAM_RAMA_END_CNTL2_G 5604 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x101a
mmCM2_CM_DGAM_RAMA_END_CNTL2_G 4666 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x101a