mmCM2_CM_DGAM_RAMA_END_CNTL1_R 4655 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0f05
mmCM2_CM_DGAM_RAMA_END_CNTL1_R 5606 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x101b
mmCM2_CM_DGAM_RAMA_END_CNTL1_R 4668 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x101b