mmCM2_CM_DGAM_RAMA_END_CNTL1_G 4651 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0f03
mmCM2_CM_DGAM_RAMA_END_CNTL1_G 5602 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x1019
mmCM2_CM_DGAM_RAMA_END_CNTL1_G 4664 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x1019