mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 4648 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 5599 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 4661 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2