mmCM2_CM_DGAM_RAMA_END_CNTL1_B 4647 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0f01
mmCM2_CM_DGAM_RAMA_END_CNTL1_B 5598 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x1017
mmCM2_CM_DGAM_RAMA_END_CNTL1_B 4660 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x1017