mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 4634 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 5585 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 4647 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2