mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 4381 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 5221 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 4283 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2