mmCM1_CM_MEM_PWR_STATUS2 5338 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f4a
mmCM1_CM_MEM_PWR_STATUS2 4400 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f4a