mmCM1_CM_MEM_PWR_STATUS 4380 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0e4e
mmCM1_CM_MEM_PWR_STATUS 5220 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f0e
mmCM1_CM_MEM_PWR_STATUS 4282 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f0e