mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 4379 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 5219 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 4281 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2