mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 5337 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 4399 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2