mmCM1_CM_ICSC_CONTROL 4104 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_ICSC_CONTROL                                                                          0x0dc4
mmCM1_CM_ICSC_CONTROL 4948 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_ICSC_CONTROL                                                                          0x0e86
mmCM1_CM_ICSC_CONTROL 4010 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_ICSC_CONTROL                                                                          0x0e86