mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 4205 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 5057 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 4119 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2