mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 4203 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 5055 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 4117 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2