mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 4217 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 5069 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 4131 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2