mmCM1_CM_DGAM_RAMA_START_CNTL_R 4164 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_R                                                                0x0de2
mmCM1_CM_DGAM_RAMA_START_CNTL_R 5016 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_R                                                                0x0ea8
mmCM1_CM_DGAM_RAMA_START_CNTL_R 4078 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_R                                                                0x0ea8