mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 4163 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 5015 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 4077 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2