mmCM1_CM_DGAM_RAMA_START_CNTL_G 4162 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_G                                                                0x0de1
mmCM1_CM_DGAM_RAMA_START_CNTL_G 5014 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_G                                                                0x0ea7
mmCM1_CM_DGAM_RAMA_START_CNTL_G 4076 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_START_CNTL_G                                                                0x0ea7