mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 4167 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 5019 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 4081 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2