mmCM1_CM_DGAM_RAMA_END_CNTL2_R 4182 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0deb
mmCM1_CM_DGAM_RAMA_END_CNTL2_R 5034 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0eb1
mmCM1_CM_DGAM_RAMA_END_CNTL2_R 4096 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0eb1