mmCM1_CM_DGAM_RAMA_END_CNTL2_G 4178 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0de9
mmCM1_CM_DGAM_RAMA_END_CNTL2_G 5030 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0eaf
mmCM1_CM_DGAM_RAMA_END_CNTL2_G 4092 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0eaf