mmCM1_CM_DGAM_RAMA_END_CNTL2_B 4174 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0de7
mmCM1_CM_DGAM_RAMA_END_CNTL2_B 5026 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0ead
mmCM1_CM_DGAM_RAMA_END_CNTL2_B 4088 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0ead