mmCM1_CM_DGAM_RAMA_END_CNTL1_R 4180 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0dea
mmCM1_CM_DGAM_RAMA_END_CNTL1_R 5032 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0eb0
mmCM1_CM_DGAM_RAMA_END_CNTL1_R 4094 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0eb0