mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 4177 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 5029 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 4091 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2