mmCM1_CM_DGAM_RAMA_END_CNTL1_G 4176 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0de8
mmCM1_CM_DGAM_RAMA_END_CNTL1_G 5028 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0eae
mmCM1_CM_DGAM_RAMA_END_CNTL1_G 4090 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0eae