mmCM1_CM_DGAM_RAMA_END_CNTL1_B 4172 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0de6
mmCM1_CM_DGAM_RAMA_END_CNTL1_B 5024 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0eac
mmCM1_CM_DGAM_RAMA_END_CNTL1_B 4086 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0eac