mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 4158 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0ddf
mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 5010 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0ea5
mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 4072 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0ea5