mmCM1_CM_DGAM_CONTROL_BASE_IDX 4153 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_DGAM_CONTROL_BASE_IDX                                                                 2
mmCM1_CM_DGAM_CONTROL_BASE_IDX 5005 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_DGAM_CONTROL_BASE_IDX                                                                 2
mmCM1_CM_DGAM_CONTROL_BASE_IDX 4067 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_DGAM_CONTROL_BASE_IDX                                                                 2