mmCM1_CM_CONTROL_BASE_IDX 4059 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
mmCM1_CM_CONTROL_BASE_IDX 4947 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
mmCM1_CM_CONTROL_BASE_IDX 4009 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_CONTROL_BASE_IDX                                                                      2