mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 5102 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ed3
mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 4164 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ed3