mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 5122 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0edd
mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 4184 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0edd