mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 5112 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0ed8
mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 4174 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0ed8