mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 5349 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 4411 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2