mmCM0_CM_MEM_PWR_STATUS 3904 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0d33
mmCM0_CM_MEM_PWR_STATUS 4646 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0da3
mmCM0_CM_MEM_PWR_STATUS 3708 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0da3