mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 3903 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 4645 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 3707 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2