mmCM0_CM_MEM_PWR_CTRL 3902 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0d32
mmCM0_CM_MEM_PWR_CTRL 4644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0da2
mmCM0_CM_MEM_PWR_CTRL 3706 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0da2