mmCM0_CM_ICSC_CONTROL_BASE_IDX 3629 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_ICSC_CONTROL_BASE_IDX                                                                 2
mmCM0_CM_ICSC_CONTROL_BASE_IDX 4375 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_ICSC_CONTROL_BASE_IDX                                                                 2
mmCM0_CM_ICSC_CONTROL_BASE_IDX 3437 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_ICSC_CONTROL_BASE_IDX                                                                 2