mmCM0_CM_ICSC_C33_C34_BASE_IDX 3641 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_ICSC_C33_C34_BASE_IDX                                                                 2
mmCM0_CM_ICSC_C33_C34_BASE_IDX 4387 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_ICSC_C33_C34_BASE_IDX                                                                 2
mmCM0_CM_ICSC_C33_C34_BASE_IDX 3449 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_ICSC_C33_C34_BASE_IDX                                                                 2