mmCM0_CM_ICSC_C31_C32_BASE_IDX 3639 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_ICSC_C31_C32_BASE_IDX                                                                 2
mmCM0_CM_ICSC_C31_C32_BASE_IDX 4385 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_ICSC_C31_C32_BASE_IDX                                                                 2
mmCM0_CM_ICSC_C31_C32_BASE_IDX 3447 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_ICSC_C31_C32_BASE_IDX                                                                 2