mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 3747 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 4501 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 3563 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2