mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 3741 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 4495 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 3557 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2