mmCM0_CM_DGAM_RAMA_START_CNTL_R 3688 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_R                                                                0x0cc7
mmCM0_CM_DGAM_RAMA_START_CNTL_R 4442 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_R                                                                0x0d3d
mmCM0_CM_DGAM_RAMA_START_CNTL_R 3504 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_R                                                                0x0d3d