mmCM0_CM_DGAM_RAMA_START_CNTL_G 3686 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_G                                                                0x0cc6
mmCM0_CM_DGAM_RAMA_START_CNTL_G 4440 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_G                                                                0x0d3c
mmCM0_CM_DGAM_RAMA_START_CNTL_G 3502 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_G                                                                0x0d3c