mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 3685 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 4439 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 3501 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2