mmCM0_CM_DGAM_RAMA_START_CNTL_B 3684 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_B                                                                0x0cc5
mmCM0_CM_DGAM_RAMA_START_CNTL_B 4438 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_B                                                                0x0d3b
mmCM0_CM_DGAM_RAMA_START_CNTL_B 3500 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_START_CNTL_B                                                                0x0d3b